? semiconductor components industries, llc, 2010 june, 2010 ? rev. 4 1 publication order number: nb4n111k/d nb4n111k 3.3v differential in 1:10 differential fanout clock driver with hcsl level output description the nb4n111k is a differential input clock 1 to 10 hcsl fanout buffer, optimized for ultra low propagation delay variation. the nb4n111k is designed with hcsl clock distribution for fbdimm applications in mind. inputs can accept differential lvpecl, cml, or lvds levels. single ? ended lvpecl, cml, lvcmos or lvttl levels are accepted with the proper v refac supply (see figures 5, 10, 11, 12, and 13). clock input pins incorporate an internal 50 on die termination resistors. outputs can interface with lvds with proper termination (see figure 15). the nb4n111k specifically guarantees low output?to?output skews. optimal design, layout, and processing minimize skew within a device and from device to device. system designers can take advantage of the nb4n111k?s performance to distribute low skew clocks across the backplane or the motherboard. features ? typical input clock frequencies: 100, 133, 166, 200, 266, 333, and 400 mhz ? 340 ps typical rise and fall times ? 800 ps typical propagation delay ? tpd 100 ps maximum propagation delay variation per each differential pair ? <1 ps rms additive clock jitter ? operating range: v cc = 3.0 v to 3.6 v with v ee = 0 v ? differential hcsl output level or lvds with proper termination ? these are pb ? free devices a = assembly site wl = wafer lot yy = year ww = work week g = pb ? free package *for additional marking information, refer to application note and8002/d. qfn32 mn suffix case 488am marking diagram* http://onsemi.com nb4n 111k awlyywwg 1 32 figure 1. pin configuration (top view) q0 q0 q1 q1 q8 q8 q9 q9 clk clk v cc gnd r ref i ref see detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. ordering information vtclk vtclk 32 1
nb4n111k http://onsemi.com 2 figure 2. pinout configuration (top view) vcc q0 q1 q1 q2 q2 vcc i ref vcc q3 q9 q5 vcc vcc q8 q7 q8 q7 1 2 3 4 5 6 7 8 vtclk clk clk vtclk q9 gnd 9 10 11 12 13 14 15 16 q6 q6 vcc 24 23 22 21 20 19 18 17 q5 q4 q4 q3 32 31 30 29 28 27 26 25 q0 exposed pad (ep) nb4n111k table 1. pin description pin name i/o description 1 i ref output output current programming pin. connect to gnd. (see figure 9). 2, 5 vtclk, vtclk ? internal 50 termination resistor connection pins. in the differential configuration when the input termination pins are connected to the common termination voltage, and if no signal is applied then the device may be susceptible to self ? oscillation. 3 clk lvpecl input clock input (true) 4 clk lvpecl input clock input (invert) 8 gnd ? supply ground. gnd pin must be externally connected to power supply to guarantee proper operation. 9, 16, 17, 24, 25, 32 v cc ? positive supply pins. v cc pins must be externally connected to a power supply to guarantee proper operation. 6, 10, 12, 14, 18, 20, 22, 26, 28, 30 q[09 ? 0] hcsl or lvds output noninverted clock output. (for lvds levels see figure 15) 7, 11, 13, 15, 19, 21, 23, 27, 29, 31 q[09 ? 0] hcsl or lvds output inverted clock output. (for lvds levels see figure 15) exposed pad ep gnd exposed pad. the thermally exposed pad (ep) on package bottom (see case drawing) must be attached to a sufficient heat ? sinking conduit for proper thermal operation. (note 1) 1. the exposed pad must be connected to the circuit board ground.
nb4n111k http://onsemi.com 3 table 2. attributes characteristic value input default state resistors none esd protection human body model >2 kv moisture sensitivity (note 2) qfn32 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 622 meets or exceeds jedec spec eia/jesd78 ic latchup test 2. for additional information, see application note and8003/d. table 3. maximum ratings (note 3) symbol parameter condition 1 condition 2 rating unit v cc positive power supply gnd = 0 v 6.0 v v i positive input gnd = 0 v gnd ? 0.3 v i v cc v v inpp differential input voltage |clk ? clk | v cc v i out output current continuous surge 50 100 ma ma t a operating temperature range qfn32 ? 40 to +70 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 3) 0 lfpm 500 lfpm qfn32 qfn32 31 27 c/w c/w jc thermal resistance (junction ? to ? case) 2s2p (note 4) qfn32 12 c/w t sol wave solder pb ? free 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 3. jedec standard 51 ? 6, multilayer board ? 2s2p (2 signal, 2 power). 4. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
nb4n111k http://onsemi.com 4 table 4. dc characteristics (v cc = 3.0 v to 3.6 v, t a = ? 40 c to +70 c note 5) symbol characteristic min typ max unit i gnd gnd supply current (all outputs loaded) 70 98 120 ma i cc power supply current (all outputs loaded) 300 ma i ih input high current clkx, clkx 2.0 150 a i il input low current clkx, clkx ? 150 ? 2.0 a differential input driven single ? ended (figures 5 and 7) v th input threshold reference voltage range (note 6) 1050 v cc ? 150 mv v ih single ? ended input high voltage v th + 150 v cc mv v il single ? ended input low voltage gnd v th ? 150 mv differential inputs driven differentially (figures 6 and 8) v ihd differential input high voltage 1200 v cc mv v ild differential input low voltage gnd v cc ? 75 mv v id differential input voltage (v ihd ? v ild ) 75 2400 mv v cmr input common mode range 1163 v cc ? 75 hcsl outputs (figure 4) v oh output high voltage 600 740 900 mv v ol output low voltage ? 150 0 150 mv note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. input parameters vary 1:1 with v cc . measurements taken with all outputs loaded 50 to gnd, see figure 9. 6. v th is applied to the complementary input when operating in single ended mode.
nb4n111k http://onsemi.com 5 table 5. ac characteristics v cc = 3.0 v to 3.6 v, gnd = 0 v; ? 40 c to +70 c (note 7) symbol characteristic min typ max unit v outpp output voltage amplitude (@ v inppmin ) f in = 400 mhz 725 1000 mv t plh , t phl propagation delay to (see figure 3) clk/clk to qx/qx 550 800 1100 ps t plh , t phl propagation delay variations variation per each diff pair clk/clk to qx/qx (note 8) (see figure 3) 100 ps t skew duty cycle skew (note 9) within ? device skew device ? to ? device skew (note 10) 20 100 150 ps ps ps t jitter rms random clock jitter (note 11) f in = 400 mhz 1 ps v cross absolute crossing magnitude voltage 250 550 mv v cross variation in magnitude of v cross 150 mv t r , t f absolute magnitude in output risetime and falltime qx, qx (from 175 mv to 525 mv) 175 340 700 ps t r, t f variation in magnitude of risetime and falltime (single ? ended) qx, qx (see figure 4) 125 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. measured by forcing v inpp (min) from a 50% duty cycle clock source. measurements taken with all outputs loaded 50 to gnd, see figure 9. typical gain is 20 db. 8. measured from the input pair crosspoint to each single output pair crosspoint across temp and voltage ranges. 9. duty cycle skew is measured between differential outputs using the deviations of the sum of tpw ? and tpw+. 10. skew is measured between outputs under identical transition @ 400 mhz. 11. additive rms jitter with 50% duty cycle clock signal using phase noise integrated from 12 khz to 33 mhz figure 3. ac reference measurement clk clk q q t plh t phl v inpp = v ih (clk) ? v il (clk) = v ih (clk ) ? v il (clk ) v outpp = v oh (q) ? v ol (q) = v oh (q ) ? v ol (q ) t plh t phl
nb4n111k http://onsemi.com 6 figure 4. hcsl output parameter characteristics 525 mv v cross v cross 175 mv t r t f clk v th clk v th figure 5. differential input driven single ? ended (v th = v refac ) clk clk figure 6. differential inputs driven differentially v ihmax v ilmax v ih v th v il v ihmin v ilmin v cc v thmax v thmin gnd v th v ihdmax v ildmax v ihdmin v ildmin v ihdtyp v ildtyp v id = v ihd ? v ild v cmr v cc v cmmax v cmmin gnd figure 7. v th diagram figure 8. v cmr diagram
nb4n111k http://onsemi.com 7 figure 9. typical termination configuration for output driver and device evaluation c lx for test only (representing receiver input loading); not added to application a . connect iref pin to gnd. b . rs1, rs2: 0 for test and evaluation. select to minimizing ringing. c . cl1, cl2: receiver input simulation load capacitance only. cl1 c 2 pf cl2 c 2 pf z 0 = 50 z 0 = 50 receiver r s1 b r s2 b hcsl driver i ref a r l1 50 r l2 50 qx qx 50 v tclk = v tclk = v cc ? 2.0 v lvpecl driver z 0 = 50 z 0 = 50 v cc = 3.3 v v cc = 3.3 v gnd gnd 50 v tclk v tclk d d figure 10. lvpecl interface *rtin, internal input termination resistor 50 v tclk = v tclk lvds driver z 0 = 50 z 0 = 50 v cc = 3.3 v v cc = 3.3 v gnd gnd 50 v tclk v tclk d d figure 11. lvds interface *rtin, internal input termination resistor nb4n111k nb4n111k
nb4n111k http://onsemi.com 8 50 v tclk = v tclk = v cc cml driver z 0 = 50 z 0 = 50 v cc v cc gnd gnd 50 v tclk v tclk d d figure 12. standard 50 load cml interface *rtin, internal input termination resistor nb4n111k v cc 50 v tclk = open lvcmos/ lvttl driver z 0 = 50 v cc v cc gnd gnd 50 v tclk v tclk d d *rtin, internal input termination resistor nb4n111k figure 13. lvcmos/lvttl interface d = v th v th v tclk = open vdr intq vcc intqb q qb figure 14. hcsl output structure figure 15. hcsl interface termination to lvds z o = 50 z o = 50 r l = 150 r l = 150 hcsl driver lvds receive qx qx 100 100
nb4n111k http://onsemi.com 9 ordering information device package shipping ? nb4n111kmng qfn32 (pb ? free) 79 units / rail NB4N111KMNR4G qfn32 (pb ? free) 1000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nb4n111k http://onsemi.com 10 package dimensions qfn32 5x5, 0.5p case 488am ? 01 issue o seating 32 x k 0.15 c (a3) a a1 d2 b 1 9 16 17 32 2 x 2 x e2 32 x 8 24 32 x l 32 x bottom view exposed pad top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e a 0.10 b c 0.05 c notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm terminal 4. coplanarity applies to the exposed pad as well as the terminals. plane dim min nom max millimeters a 0.800 0.900 1.000 a1 0.000 0.025 0.050 a3 0.200 ref b 0.180 0.250 0.300 d 5.00 bsc d2 2.950 3.100 3.250 e 5.00 bsc e2 e 0.500 bsc k 0.200 ??? ??? l 0.300 0.400 0.500 2.950 3.100 3.250 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 pitch 3.20 0.28 3.20 32 x 28 x 0.63 32 x 5.30 5.30 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 nb4n111k/d the products described herein (nb4n111k), may be covered by u.s. patents including 6,362,644 . there may be other patents pending. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
|
